1. Field of the Invention
The invention relates to an image scaler and method of the same, and more particular to an image scaler that can generate a high quality scaled image with a simplified circuit layout.
2. Description of the Related Art
Conventional techniques for monitor hardware are mature, and various image-scaling techniques for monitors are well developed, as well. For example, with reference to FIG. 7, U.S. Pat. No. 5,739,867 of “Methods and apparatus for upscaling an image in both horizontal and vertical directions” shows a preferred embodiment which includes an input data synchronizer 50, a first buffer area 51, a first-in first-out memory (hereafter abbreviated as FIFO) 52, a second buffer area 53, a vertical interpolator 54, and a horizontal interpolator 55. The first buffer area 51 includes a plurality of line buffers having an input terminal coupled to the input data synchronizer 50. The FIFO 52 outputs data according to the principle of first-in first-out. The second buffer area 53 includes a plurality of line buffers having an input terminal coupled to the FIFO 52. The vertical interpolator 54 includes an input terminal coupled respectively to a data output terminal of the FIFO 52 and an output terminal of the second buffer area 53. The horizontal interpolator 55 is coupled to an output terminal of the vertical interpolator 54.
The synchronization technique applied in image scaling techniques is very important. In the above described image upscaler structure of the preferred embodiment of the U.S. patent, input image data is first inputted to be synchronized, sent to the FIFO 52, and then upscaled in the vertical and horizontal directions.
According to the above arranged structure, when the image data is inputted, the image data is synchronized first. Then the image data is processed to be vertically and horizontally upscaled by the vertical interpolator 54 and the horizontal interpolator 55, respectively.
It can be understood according to FIG. 7 that a data processing frequency of the input data synchronizer 50 and the first buffer area 51 is determined by an input clock frequency. After processing by the input data synchronizer 50 and the first buffer area 51, an intermediate clock frequency is sent out, so that the FIFO 52, the second buffer area 53 and the vertical interpolator 54 operate under the intermediate clock frequency. Finally the horizontal interpolator 55 sends out the final output clock frequency. This design makes most of the components operate under the intermediate clock frequency, which has the drawbacks of having a high working frequency, heavy loading with huge amounts of data and high cost.
Moreover, U.S. Pat. No. 6,611,260 of “Ultra-high bandwidth multi-port memory system for image scaling application” is taken as another example. This patent discloses an image scaling memory system which eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scaler with simultaneous parallel access to multiple lines of data.
With reference to FIG. 8, a preferred embodiment of the U.S. Pat. No. 6,611,260 includes a first stage vertical image scaling circuit 60 and a second stage horizontal image scaling circuit 61. When image data is inputted, the vertical image scaling circuit 60 first upscales a vertical signal of the image data, then the horizontal image scaling circuit 61 upscales a horizontal signal of the image data. Thereby the horizontal image scaling circuit 61 processes more data volume than the vertical image scaling circuit 60 does. Hence the horizontal image scaling circuit 61 requires a clock frequency that is higher than an output clock frequency O-CLK of an input clock frequency S-CLK to process the input image data. In addition, the horizontal image scaling circuit 61 requires a clock frequency that is even higher than an intermediate frequency M-CLK, so as to be able to speed up the outputting of the upscaled image data.
Therefore, it can be understood from the above two examples of the U.S. patents that the conventional techniques mainly focus on improving the buffer areas of an image scaler. However, the conventional techniques do not concentrate on the research and development to reduce the number working clock frequencies, as the two examples both require three different clock frequencies. Hence the conventional techniques tend to have complicated circuit designs, consume much power and have high design costs.